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Cake day: July 2nd, 2023

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  • Micay stepped down as lead developer and foundation director. I’m not sure what role he has with the project currently, but it seems like he plans on leaving the project entirely, long term. I haven’t heard of any controversy since then. They’ve been hard at work and actually added support for Android Auto last month.


    • SLC -> Single-Level Cell, i.e. 1 bit per cell
    • MLC -> Multi-Level Cell, i.e. 2 bits per cell
    • TLC -> Triple-Level Cell, i.e. 3 bits per cell
    • QLC -> Quad-Level Cell, i.e. 4 bits per cell

    The more bits per cell you store, the more dense and therefore cheaper your flash chips can be for a give capacity. The downside is that it is slower and less reliable since you have to be able to write and read exponentially more voltage states per cell, e.g. 2 states for SLC, 4 states for MLC, 8 states for TLC, etc.


  • USB 2 is 480 Mb/s, not 480 MB/s. 480 Mb/s is 60 MB/s, so the 500 MB/s from PCIe 2.0 x1 is quite a bit faster and is about the limit of what a SATA 3 interface could do. Also, sequential throughput isn’t nearly as important as most people think. Random IO, which NVMe drives excel at, will make a far more noticeable impact on real world performance.